10CL040YU484I7G vs 10CL055YU484I7G 对比

详细并排对比 10CL040YU484I7G 出自 Intel 和 10CL055YU484I7G 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 10CL040YU484I7G 10CL055YU484I7G
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $48.75 $35.10
Family Cyclone 10 LP Cyclone 10 LP
Logic Elements (LE) 39,600 —
Configurable Logic Blocks (CLB) 2,475 —
Embedded Memory 1,161,216 bits (M9K blocks) —
Embedded 18x18 Multipliers 66 —
Maximum User I/O 325 —
General-Purpose PLLs 4 —
Core Voltage 1.0 V to 1.2 V —
工作温度 -40 C to +100 C (Industrial) —
封装 484-pin UBGA (Ultra FineLine BGA) 484-ball UBGA (Ultra FineLine BGA), 19 mm x 19 mm
Ball Pitch 0.8 mm —
Process Technology TSMC 60 nm low-power 60 nm low-power CMOS
安装类型 Surface Mount —
Configuration Mode JTAG / AS / PS —
RoHS 状态 Compliant Compliant
Supply Form Tray —
Logic Elements — 55,856
Embedded Memory Bits — 2,396,160 bits
M9K Memory Blocks — 260
Maximum User I/Os — 321
DSP Blocks (18x18 multipliers) — 156
PLLs — 4
Global Clock Networks — 20
Speed Grade — -7 (I7, industrial)
工作结温 — -40C to +100C
Core Voltage (VCCINT) — 1.0V (typical), 1.1V nominal
I/O Voltage (VCCIO) — 1.2V to 3.3V (bank-dependent)
Configuration Modes — JTAG, AS, PS, FPP
LVDS Data Rate — Up to 875 Mbps per channel
MSL 等级 — 3 (per JEDEC J-STD-020)

数据手册与资源

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