10CL055YF484I7G vs 10CL055YU484C6G 对比
详细并排对比 10CL055YF484I7G 出自 Intel 和 10CL055YU484C6G 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | 10CL055YF484I7G | 10CL055YU484C6G |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $46.09 | $24.38 |
| Series | Cyclone 10 LP | — |
| Family | Cyclone® 10 LP | Cyclone 10 LP |
| Logic Elements (LE) | 55,856 | 55,856 |
| Embedded Memory (bits) | 2,396,160 | — |
| Number of Logic Array Blocks (LAB) | 3,478 | — |
| Number of M9K Memory Blocks | 260 | — |
| Embedded Multipliers (18x18) | 156 | — |
| Maximum User I/Os | 321 | 321 |
| Number of PLLs | 4 | — |
| Global Clock Networks | 20 | — |
| 工作温度 | -40C to +100C (Industrial) | 0 C to +85 C (commercial, C suffix) |
| Speed Grade | I7 | 6 (commercial, slowest in family) |
| 封装 | 484-BGA (FBGA, FineLine BGA) | 484-pin UBGA (19 mm x 19 mm) |
| 安装类型 | Surface Mount | Surface Mount |
| Configuration Method | Active Serial (AS), Passive Serial (PS), JTAG | — |
| Core Voltage | 1.2 V | 1.0 V (typical) |
| Auxiliary Voltage | 2.5 V / 3.3 V | — |
| RoHS 状态 | Compliant | Compliant |
| Process Technology | 60 nm low-power CMOS | TSMC 60 nm low-power |
| Hard Memory Controller | DDR2 / DDR3 / LPDDR2 | Yes (DDR/DDR2/DDR3/LPDDR2 via soft IP) |
| Embedded Memory Bits | — | 2,396,160 bits (approximately 2.5 Mb) |
| Embedded 18x18 Multipliers | — | 156 |
| PLLs | — | 4 |
| Global Clocks | — | 20 |
| I/O Voltage Standards | — | LVDS, LVTTL, LVCMOS, SSTL, HSTL (1.2 V to 3.3 V) |
| MSL 等级 | — | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Lead-Free / Halogen-Free | — | Yes / [DATA_NEEDED: halogen-free status] |
| Configuration Modes | — | Active Serial (AS), Passive Serial (PS), JTAG |
| Transceivers | — | None (Cyclone 10 LP family does not include SERDES) |