10CL055YU484C6G vs 10CL080YU484C6G 对比

详细并排对比 10CL055YU484C6G 出自 Altera 和 10CL080YU484C6G 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 10CL055YU484C6G 10CL080YU484C6G
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $24.38 $34.75
Family Cyclone 10 LP Cyclone 10 LP
Logic Elements (LE) 55,856 81,264
Embedded Memory Bits 2,396,160 bits (approximately 2.5 Mb) 2,810,880 bits
Maximum User I/Os 321 —
Embedded 18x18 Multipliers 156 —
PLLs 4 4
Global Clocks 20 —
Core Voltage 1.0 V (typical) 1.0 V / 1.2 V (selectable)
I/O Voltage Standards LVDS, LVTTL, LVCMOS, SSTL, HSTL (1.2 V to 3.3 V) —
Speed Grade 6 (commercial, slowest in family) -6 (C6)
封装 484-pin UBGA (19 mm x 19 mm) 484-pin UBGA (UBGA-484), 19x19 mm, 0.8 mm pitch
Process Technology TSMC 60 nm low-power 60 nm TSMC low-power
工作温度 0 C to +85 C (commercial, C suffix) 0C to +85C (Commercial)
安装类型 Surface Mount Surface Mount (BGA)
MSL 等级 [DATA_NEEDED: MSL level per JEDEC J-STD-020] —
RoHS 状态 Compliant Compliant
Lead-Free / Halogen-Free Yes / [DATA_NEEDED: halogen-free status] —
Configuration Modes Active Serial (AS), Passive Serial (PS), JTAG AS, PS, JTAG, FPP
Transceivers None (Cyclone 10 LP family does not include SERDES) —
Hard Memory Controller Yes (DDR/DDR2/DDR3/LPDDR2 via soft IP) —
Embedded Memory Blocks — M9K (true dual-port)
18x18 Hardware Multipliers — 244
Maximum User I/O — 289
External Memory Support — DDR2, DDR3, LPDDR2

数据手册与资源

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