10CL055YU484I7G vs 10CL055YU484C6G 对比
详细并排对比 10CL055YU484I7G 出自 Altera 和 10CL055YU484C6G 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | 10CL055YU484I7G | 10CL055YU484C6G |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $35.10 | $24.38 |
| Family | Cyclone 10 LP | Cyclone 10 LP |
| Logic Elements | 55,856 | — |
| Embedded Memory Bits | 2,396,160 bits | 2,396,160 bits (approximately 2.5 Mb) |
| M9K Memory Blocks | 260 | — |
| Maximum User I/Os | 321 | 321 |
| DSP Blocks (18x18 multipliers) | 156 | — |
| PLLs | 4 | 4 |
| Global Clock Networks | 20 | — |
| Process Technology | 60 nm low-power CMOS | TSMC 60 nm low-power |
| 封装 | 484-ball UBGA (Ultra FineLine BGA), 19 mm x 19 mm | 484-pin UBGA (19 mm x 19 mm) |
| Speed Grade | -7 (I7, industrial) | 6 (commercial, slowest in family) |
| 工作结温 | -40C to +100C | — |
| Core Voltage (VCCINT) | 1.0V (typical), 1.1V nominal | — |
| I/O Voltage (VCCIO) | 1.2V to 3.3V (bank-dependent) | — |
| Configuration Modes | JTAG, AS, PS, FPP | Active Serial (AS), Passive Serial (PS), JTAG |
| LVDS Data Rate | Up to 875 Mbps per channel | — |
| RoHS 状态 | Compliant | Compliant |
| MSL 等级 | 3 (per JEDEC J-STD-020) | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Logic Elements (LE) | — | 55,856 |
| Embedded 18x18 Multipliers | — | 156 |
| Global Clocks | — | 20 |
| Core Voltage | — | 1.0 V (typical) |
| I/O Voltage Standards | — | LVDS, LVTTL, LVCMOS, SSTL, HSTL (1.2 V to 3.3 V) |
| 工作温度 | — | 0 C to +85 C (commercial, C suffix) |
| 安装类型 | — | Surface Mount |
| Lead-Free / Halogen-Free | — | Yes / [DATA_NEEDED: halogen-free status] |
| Transceivers | — | None (Cyclone 10 LP family does not include SERDES) |
| Hard Memory Controller | — | Yes (DDR/DDR2/DDR3/LPDDR2 via soft IP) |