5M1270ZT144C5N vs 5M1270ZT144C4N 对比
详细并排对比 5M1270ZT144C5N 出自 Altera 和 5M1270ZT144C4N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
5M1270ZT144C5N - MAX V CPLD 980 Macrocells 114 I/O TQFP-144 | Intel / Altera
5M1270ZT144C5N ✓ 量产中规格对比
| 参数 | 5M1270ZT144C5N | 5M1270ZT144C4N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $12.45 | $9.49 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Series | MAX V | — |
| Logic Elements | 1270 | 1270 |
| Macrocells | 980 | 980 |
| User I/Os | 114 | — |
| Maximum Internal Frequency | 118.3 MHz | 247.5 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 6.2 ns | 8.1 ns |
| Internal Frequency (typical) | 201 MHz | — |
| User Flash Memory (UFM) | 8 Kbits | Yes (on-chip, non-volatile data storage) |
| Configuration Memory | Flash (non-volatile, in-system programmable) | Non-volatile Flash |
| VCCINT (Core Supply) | 1.71 V to 1.89 V | — |
| VCCIO (I/O Supply, per bank) | 1.2 V to 3.3 V | — |
| Number of I/O Banks | 4 | — |
| Supported I/O Standards | LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins | — |
| JTAG Interface | IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1) | — |
| Programming Interface | JTAG in-system programmable (Altera Quartus II) | JTAG (IEEE 1149.1) - In-System Programmable |
| Program/Erase Cycles | Up to 100,000 | — |
| 封装 | TQFP-144 (22 x 22 mm, 0.5 mm pitch) | 144-pin TQFP (22 mm x 22 mm, 0.5 mm pitch) |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度 | 0 C to +85 C (commercial grade) | — |
| RoHS 状态 | Compliant | Compliant |
| Family | — | MAX V CPLD |
| User I/O Pins | — | 114 |
| Logic Array Blocks (LABs) | — | 8 |
| Core Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Voltage (VCCIO) | — | 1.8 V / 2.5 V / 3.3 V (multi-voltage banks) |
| Process Technology | — | 0.18 um CMOS |
| Operating Temperature Grade | — | Commercial (0C to +85C) |