5M1270ZT144I5N vs 5M1270ZT144C5N 对比

详细并排对比 5M1270ZT144I5N 出自 Intel 和 5M1270ZT144C5N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 5M1270ZT144I5N 5M1270ZT144C5N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $17.90 $12.45
Family MAX V —
Device Logic Elements 980 —
Number of Macro Cells 980 —
Maximum User I/O Pins 212 —
Number of Logic Array Blocks (LABs) 61 —
User Flash Memory 8 Kbits —
Maximum Operating Frequency 201.1 MHz —
Pin-to-Pin Delay (tPD) 1.5 ns (max) —
Core Supply Voltage (VCCINT) 1.8 V —
I/O Supply Voltage (VCCIO) 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V (multi-voltage) —
工作温度 -40C to +100C (Industrial) 0 C to +85 C (commercial grade)
封装 144-pin TQFP (T144) TQFP-144 (22 x 22 mm, 0.5 mm pitch)
安装类型 Surface Mount Surface Mount
Configuration Method Non-volatile flash, in-system programmable —
Programmable Via JTAG (IEEE 1149.1) / Quartus Prime —
Device Type — CPLD (Complex Programmable Logic Device)
Series — MAX V
Logic Elements — 1270
Macrocells — 980
User I/Os — 114
Maximum Internal Frequency — 118.3 MHz
Pin-to-Pin Propagation Delay (tPD) — 6.2 ns
Internal Frequency (typical) — 201 MHz
User Flash Memory (UFM) — 8 Kbits
Configuration Memory — Flash (non-volatile, in-system programmable)
VCCINT (Core Supply) — 1.71 V to 1.89 V
VCCIO (I/O Supply, per bank) — 1.2 V to 3.3 V
Number of I/O Banks — 4
Supported I/O Standards — LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins
JTAG Interface — IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1)
Programming Interface — JTAG in-system programmable (Altera Quartus II)
Program/Erase Cycles — Up to 100,000
RoHS 状态 — Compliant

数据手册与资源

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