5M240ZM68C5N vs 5M160ZM68C5N 对比
详细并排对比 5M240ZM68C5N 出自 Intel 和 5M160ZM68C5N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | 5M240ZM68C5N | 5M160ZM68C5N |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.05 | $3.12 |
| Series | MAX V | 5M160Z |
| Family | MAX V (5M240Z) | MAX V CPLD |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Architecture | Non-volatile flash-based | — |
| Macro Cells | 192 | — |
| Logic Elements | 240 | — |
| Logic Array Blocks (LABs) | 4 | — |
| Maximum Operating Frequency | 118.3 MHz | 118.3 MHz |
| Core Supply Voltage | 1.8 V (1.71 V to 1.89 V) | 1.8 V |
| I/O Banks | MultiVolt I/O, 1.5/1.8/2.5/3.3 V compatible | — |
| Global Clocks | 4 | — |
| User Flash Memory | Yes (integrated) | 8 Kbits |
| 封装 | 68-ball Micro FBGA (BGA-68) | — |
| 安装类型 | Surface Mount | — |
| 工作温度 | 0 °C to +85 °C (commercial) | — |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG (IEEE Std. 1149.1), in-system programmable |
| RoHS 状态 | Compliant | Compliant |
| Macrocells | — | 128 |
| Logic Elements (typical) | — | 160 |
| Pin-to-Pin Logic Delay | — | 7.5 ns |
| Number of Logic Array Blocks (LABs) | — | 4 |
| I/O Standards Supported | — | LVTTL, LVCMOS 1.5/1.8/2.5/3.3 V |
| Package Type | — | 68-ball Micro FineLine BGA (MBGA) |
| 工作温度范围 | — | 0C to +85C (commercial) |
| Configuration Memory | — | Non-volatile flash (instant-on, no boot PROM required) |
| Internal Oscillator | — | Yes (on-chip) |
| Lead-Free | — | Yes |
| MSL 等级 | — | [DATA_NEEDED: MSL level] |