5M40ZE64C5N vs 5M40ZE64C4N 对比

详细并排对比 5M40ZE64C5N 出自 Altera 和 5M40ZE64C4N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 5M40ZE64C5N 5M40ZE64C4N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $4.85 $1.70
Series MAX V —
Device Type CPLD - Complex Programmable Logic Device —
Logic Elements (LE) 40 32
Macrocells 32 —
Maximum User I/Os 54 —
Propagation Delay (tPD1) 7.5 ns —
Maximum Internal Frequency 118.3 MHz 184 MHz
Configuration Memory Flash (non-volatile) Non-volatile flash (internal)
Supply Voltage - Core 1.8 V (internal) —
External Supply Voltage 3.3 V —
I/O Voltage Support 1.5 V / 1.8 V / 2.5 V / 3.3 V LVCMOS, LVTTL —
Programming Interface JTAG (IEEE 1149.1) - in-system programmable JTAG (IEEE 1149.1)
封装 64-pin EQFP (Plastic Enhanced Thin QFP) with exposed thermal pad EQFP-64 (Plastic Enhanced QFP, 64 pins)
安装类型 Surface Mount Surface Mount
工作温度 0C to +85C (commercial) 0 °C to +85 °C (commercial)
User Flash Memory (UFM) Yes (on-chip non-volatile) —
RoHS 状态 [DATA_NEEDED: RoHS compliance status] Compliant
Family — MAX V
User Flash Memory — 4 Kbit
Pin-to-Pin Delay (tPD1) — 7.5 ns
Number of I/O Pins — 30 (approx.)
Supply Voltage (VCCINT) — 1.8 V
I/O Bank Voltage — 1.8 V / 2.5 V / 3.3 V
Process Technology — 0.18 µm flash-based CMOS
Programmable Pull-up Resistors — Yes (per-pin, internal)
MSL 等级 — 3 (per JEDEC J-STD-020)

数据手册与资源

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