5M570ZT144C5N vs 5M570ZT144C4N 对比

详细并排对比 5M570ZT144C5N 出自 Altera 和 5M570ZT144C4N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 5M570ZT144C5N 5M570ZT144C4N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $7.25 $9.85
Family MAX V MAX V CPLD
Device Family MAX V CPLD —
Logic Elements 440 —
Macro Cells 440 440
Maximum Operating Frequency 118.3 MHz 184.1 MHz
Number of User I/O Pins 212 (max for MAX V family) —
User Flash Memory 8 Kbits —
Core Voltage 1.8 V —
I/O Voltage Standards 1.2 V to 3.3 V (LVCMOS, LVTTL, PCI, etc.) —
Propagation Delay [DATA_NEEDED: tPD value not in verified data] —
封装 TQFP-144 (22 mm x 22 mm, 0.5 mm pitch) 144-pin TQFP (T144)
Programming Interface JTAG (IEEE 1149.1) - in-system programmable —
Configuration Memory Non-volatile flash (instant-on, no boot PROM) Internal flash, non-volatile, ISP via JTAG
工作温度 0C to +85C (commercial grade) 0 °C to +85 °C (commercial)
安装类型 Surface Mount Surface Mount
RoHS 状态 Compliant Compliant
Supply Voltage Range 1.71 V to 1.89 V (VCCINT); 1.2 V-3.3 V (VCCIO) —
Logic Elements (LEs) — 570
User I/O Pins — 114
Pin-to-Pin Delay (tPD) — 9.5 ns
Core Supply Voltage — 1.8 V
I/O Bank Supply Voltage (VCCIO) — 1.5 V / 1.8 V / 2.5 V / 3.3 V
I/O Banks — 8
Configuration Interface — JTAG (IEEE 1149.1) / passive serial
MSL 等级 — [DATA_NEEDED: MSL level]

数据手册与资源

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