ADC12DL040CIVSX vs ADC12DL040CIVS 对比
详细并排对比 ADC12DL040CIVSX 出自 Texas Instruments 和 ADC12DL040CIVS 出自 Texas Instruments。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Texas Instruments
ADC12DL040CIVSX - Dual 12-Bit 40 MSPS ADC | Texas Instruments
ADC12DL040CIVSX ✓ 量产中Texas Instruments
ADC12DL040CIVS - Dual 12-Bit 40 MSPS 3V ADC | Texas Instruments
ADC12DL040CIVS Nrnd规格对比
| 参数 | ADC12DL040CIVSX | ADC12DL040CIVS |
|---|---|---|
| 品牌 | Texas Instruments | Texas Instruments |
| 分类 | ADC/DAC | ADC/DAC |
| 生命周期状态 | 有效 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $16.95 | $11.85 |
| 分辨率 | 12 bit | 12 Bits |
| Number of Channels | 2 (Dual) | 2 (dual, simultaneous sampling) |
| Sampling Rate (per channel) | 40 MSPS | — |
| Architecture | Pipelined CMOS | Pipelined CMOS |
| 输入电压范围 | 0.0 V to 2.6 V (analog input) | — |
| Analog Supply Voltage | 3 V (single supply) | 3.0 V (2.7 V to 3.6 V range) |
| Power Dissipation | 210 mW (typical, 3V, 40 MSPS) | — |
| Power Consumption per Channel | 105 mW (typical) | — |
| Data Interface | Parallel CMOS | — |
| Digital Output Format | [DATA_NEEDED: digital output format/code] | — |
| Reference Type | Internal (on-chip reference) | — |
| 工作温度范围 | -40C to +85C (Industrial) | — |
| 封装 / 外壳 | 64-TQFP (PAG) 10x10 mm | — |
| 安装类型 | Surface Mount | — |
| MSL 等级 | [DATA_NEEDED: MSL level] | — |
| Sample-and-Hold | Yes (integrated, per channel) | Internal, dual |
| Differential Nonlinearity (DNL) | [DATA_NEEDED: DNL bits LSB] | — |
| Integral Nonlinearity (INL) | [DATA_NEEDED: INL bits LSB] | — |
| Signal-to-Noise Ratio (SNR) | [DATA_NEEDED: SNR dB at 40 MSPS] | — |
| RoHS 状态 | Compliant | — |
| Lead-Free | Yes | — |
| Sample Rate (per channel) | — | 40 MSPS |
| Digital Output Driver Supply | — | 2.4 V to 3.6 V (separate DVDD) |
| Power Dissipation (typical) | — | 210 mW |
| Power-Down Mode | — | Yes |
| SNR (fIN = 10 MHz) | — | 69 dB (typical) |
| SFDR (fIN = 10 MHz) | — | 85 dB (typical) |
| DNL (Differential Non-Linearity) | — | ±0.3 LSB (typical) |
| INL (Integral Non-Linearity) | — | [DATA_NEEDED: INL spec] |
| Internal Reference | — | Yes (factory-trimmed, not user-adjustable) |
| Duty Cycle Stabilizer | — | Yes |
| Multiplexed Output Mode | — | Yes (channels share single 12-bit bus) |
| Output Format | — | Straight Binary, offset binary, 2's complement (per pin strapping) |
| Input Clock | — | Single-ended or differential; 50 Ω terminated internally |
| 工作温度 | — | -40 °C to +85 °C (industrial) |
| 封装 | — | 64-pin TQFP (PAG) 10x10 mm, surface-mount |
| MSL (Moisture Sensitivity Level) | — | [DATA_NEEDED: MSL level] |
| Lead Finish / RoHS | — | Lead-free / RoHS status depends on orderable suffix (see datasheet ordering info) |