ADF4153YRUZ vs ADF4156BRUZ 对比

详细并排对比 ADF4153YRUZ 出自 Analog Devices 和 ADF4156BRUZ 出自 Analog Devices。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Analog Devices
ADF4153YRUZ ADF4153YRUZ - 4 GHz Fractional-N PLL | Analog Devices

ADF4153YRUZ - 4 GHz Fractional-N PLL | Analog Devices

ADF4153YRUZ ✓ 量产中

规格对比

参数 ADF4153YRUZ ADF4156BRUZ
品牌 Analog Devices Analog Devices
分类 Clock & Timing Clock & Timing
生命周期状态 有效 有效
Device Type Fractional-N frequency synthesizer Fractional-N frequency synthesizer (PLL), single circuit
RF Bandwidth 4 GHz —
Maximum Synthesized Frequency 4 GHz —
电源电压 3.3 V —
Architecture Fractional-N phase-locked loop —
PLL Yes —
Input Signal Type CMOS —
Output Signal Type Clock —
Number of Circuits 1 —
Input-to-Output Ratio 2:1 —
Differential Input Yes —
Differential Output No —
Programmable Fractional Modulus Yes —
Programmable Charge Pump Yes —
Programmable Reference Divider Yes —
Separate VP Connection Yes, permits extended tuning voltage —
Maximum Temperature +125 °C —
封装 16-TSSOP, 4.40 mm width 16-lead TSSOP (0.173", 4.40 mm width)
安装类型 Surface mount Surface mount
Manufacturer Document Revision Rev. G —
Production Status Production —
RoHS 状态 unknown unknown
REACH Status unknown —
AEC-Q100 Qualification unknown —
Maximum RF Input Frequency — 6.2 GHz
Minimum RF Input Frequency — 500 MHz
RF Input Slew Rate Requirement — 400 V/us minimum
Fractional Interpolator Architecture — Sigma-Delta
Phase Frequency Detector — Low noise digital PFD
Charge Pump — Precision, programmable
Reference Divider — Programmable
RF Output Phase — Programmable
Cycle Slip Reduction — Supported (faster lock without loop filter changes)
Control Interface — 3-wire serial (DATA, CLK, LE)
引脚数量 — 16
Shipping Container — Tube
Power Supply Voltage — [DATA_NEEDED: supply voltage range]
工作温度范围 — [DATA_NEEDED: operating temperature range]
Lock Detect / MUXOUT — [DATA_NEEDED: lock detect output configuration]
Output Drive Level — [DATA_NEEDED: output drive level]

数据手册与资源

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