CDK1307DILP40 vs CDK1307CILP40 对比

详细并排对比 CDK1307DILP40 出自 MaxLinear 和 CDK1307CILP40 出自 MaxLinear。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

MaxLinear
CDK1307CILP40 CDK1307CILP40 - 12/13-bit 65MSPS Ultra-Low Power ADC | Exar

CDK1307CILP40 - 12/13-bit 65MSPS Ultra-Low Power ADC | Exar

CDK1307CILP40 ✓ 量产中

规格对比

参数 CDK1307DILP40 CDK1307CILP40
品牌 MaxLinear MaxLinear
分类 ADC/DAC ADC/DAC
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $9.60 $3.95
分辨率 13 bit 12-bit / 13-bit selectable
Sampling Rate (max) 80 MSPS —
Power Dissipation (typ) 60 mW at 80 MSPS —
Family Power Grades 17 / 19 / 33 / 50 / 60 / 75 mW across speed grades —
SNR 72.4 dB at Fin = 8 MHz —
Analog Supply Voltage 1.8 V (core) —
I/O Supply Voltage 1.7 V to 3.6 V —
Output Interface Parallel CMOS Parallel CMOS
Reference Internal reference circuitry Internal (1.2 V bandgap)
Clock Input Differential, low-jitter —
Track-and-Hold Highly linear, optimized to Nyquist —
Idle Modes Standby and Power Down —
封装 40-pin QFN 40-pin LQFP (LP)
Pin Compatibility Pin-compatible with CDK1308 —
Pin Compatibility (family) Same 40-pin QFN for A/B/C/D speed grades —
Part Number — CDK1307CILP40
Manufacturer — MaxLinear (formerly Exar/Cadeka)
功能 — Analog-to-Digital Converter (ADC)
Sample Rate — 65 MSPS (family supports 20/40/65/80 MSPS)
Architecture — Multi-stage pipeline with digital error correction
Input Type — Single-ended analog input
Full-Scale Input Range — 1 Vpp typical
Supply Voltage (Analog) — 3.3 V
Supply Voltage (Digital) — 3.3 V
Control Interface — CMOS serial configuration
工作温度 — -40 C to +85 C (industrial)
RoHS 状态 — Compliant

数据手册与资源

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