EP1810GM883B vs EP1810GC-35 对比

详细并排对比 EP1810GM883B 出自 Altera 和 EP1810GC-35 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EP1810GC-35 EP1810GC-35 - UV PLD, 40ns, CMOS, CPGA68 | Altera / Rochester

EP1810GC-35 - UV PLD, 40ns, CMOS, CPGA68 | Altera / Rochester

EP1810GC-35 ⚠ 最后一次采购

规格对比

参数 EP1810GM883B EP1810GC-35
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 最后采购期
库存状态 有库存 有库存
单价(USD) $125.40 $177.12
Device Family EP1810 (Classic EPLD) —
Macrocells 48 16
User Flip-Flops Up to 64 —
Total Inputs 60 —
Dedicated Inputs 12 —
I/O Pins 48 (bidirectional, tri-state) —
Propagation Delay (tPD) 50 ns max —
Supply Voltage (VCC) 4.5 V to 5.5 V —
Technology CMOS, UV-erasable CMOS, UV-erasable EPROM cells
工作温度 -55 °C to +125 °C (Military, MIL-STD-883B) [DATA_NEEDED: operating temperature range]
Package Type Ceramic Pin Grid Array (PGA), 84 pins —
Package Designator GM (ceramic PGA) —
Processing Level MIL-STD-883B (Class B) —
Programming Method UV-erasable / Altera programming hardware UV erasure + EPROM programming
安装类型 Through-hole (PGA socket or PCB through-hole) Through Hole
Lead-Free / RoHS [DATA_NEEDED: lead-free status] —
Logic Family TTL-compatible I/O Altera Classic EPLD
Device Type — EPLD (Erasable Programmable Logic Device)
封装 — CPGA-68 (Ceramic Pin Grid Array, 68-pin)
引脚数 — 68
Propagation Delay (tpd max) — 40 ns
Maximum Inputs — 64
Maximum Outputs — 48
I/O Standard — TTL-compatible
电源电压 — [DATA_NEEDED: VCC range]
RoHS 状态 — Not applicable (legacy ceramic package)
Lead-Free Status — Not applicable
Manufacturer (current source) — Rochester Electronics (authorized Altera EPLD partner)
Original Manufacturer — Altera Corporation (now Intel FPGA)

数据手册与资源

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