EP1810JC-25 vs EP1810GI-45 对比
详细并排对比 EP1810JC-25 出自 Intel 和 EP1810GI-45 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1810JC-25 | EP1810GI-45 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $6.80 | $56.40 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera/Intel Classic EPLD (EP1810 series) | Altera Classic EPLD |
| Macrocells | 48 | 24 |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: max fMAX] | — |
| Input Lines | 60 (including I/O) | — |
| I/O Lines | 48 | — |
| Dedicated Inputs | 12 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| 工作温度 | -40 °C to 85 °C (industrial, per distributor listings) | [DATA_NEEDED: operating temperature range] |
| Technology | CMOS, UV-erasable (windowed ceramic DIP) | CMOS |
| 封装 | 28-pin ceramic DIP (J) with quartz window | — |
| 安装类型 | Through-hole | Through-Hole |
| Erasure Method | UV light (windowed package) | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status] | Non-compliant (ceramic PGA) |
| 生命周期状态 | NRND (Not Recommended for New Designs) | — |
| Device Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Flip-Flops | — | 48 |
| Propagation Delay (tpd) | — | 45 ns |
| Speed Grade | — | -45 |
| Package Type | — | Ceramic Pin Grid Array with UV window |
| 引脚数量 | — | 68 |
| Programmable | — | Yes (UV-erasable, electrically programmable) |
| Lead-Free | — | No |
| 电源电压 | — | [DATA_NEEDED: VCC range] |