EP1810JC-35 vs EP1810GM883B 对比
详细并排对比 EP1810JC-35 出自 Intel 和 EP1810GM883B 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1810JC-35 | EP1810GM883B |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $5.48 | $125.40 |
| Device Family | Classic EPLD (EP1810) | EP1810 (Classic EPLD) |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) | — |
| Number of Macrocells | 48 | — |
| Propagation Delay (tpd) | 35 ns (max) | — |
| 最大时钟频率 | [DATA_NEEDED: fmax for this speed grade] | — |
| Process Technology | CMOS | — |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Maximum Supply Voltage | 5.25 V (per distributor listing) | — |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) | Ceramic Pin Grid Array (PGA), 84 pins |
| Number of Terminals | 68 | — |
| Terminal Form | J-Bend | — |
| 工作温度范围 | 0°C to 70°C (Commercial) | — |
| Temperature Grade | Commercial | — |
| Erasure Method | UV (quartz-windowed ceramic package) | — |
| RoHS 状态 | Compliant (per Altera listing) | — |
| Lead-Free Status | Lead-free (per distributor listing) | — |
| 安装类型 | Surface Mount (J-Lead) | Through-hole (PGA socket or PCB through-hole) |
| Logic Architecture | Programmable AND/OR array with macrocell outputs | — |
| Macrocells | — | 48 |
| User Flip-Flops | — | Up to 64 |
| Total Inputs | — | 60 |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 (bidirectional, tri-state) |
| Propagation Delay (tPD) | — | 50 ns max |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| Technology | — | CMOS, UV-erasable |
| 工作温度 | — | -55 °C to +125 °C (Military, MIL-STD-883B) |
| Package Designator | — | GM (ceramic PGA) |
| Processing Level | — | MIL-STD-883B (Class B) |
| Programming Method | — | UV-erasable / Altera programming hardware |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free status] |
| Logic Family | — | TTL-compatible I/O |