EP1810JI-45 vs EP1810JC-45 对比
详细并排对比 EP1810JI-45 出自 Altera 和 EP1810JC-45 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1810JI-45 | EP1810JC-45 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.75 | $21.10 |
| Manufacturer | Altera (now Intel FPGA) | — |
| Series | Classic EPLD Family | — |
| Device Type | UV-Erasable / OTP Complex PLD | — |
| Macrocell Count | 48 | — |
| Maximum Operating Frequency | 33.3 MHz | — |
| Propagation Delay (tPD) | 50 ns | — |
| Configurable I/O Lines | 48 | — |
| Dedicated Inputs | 12 | 12 |
| Technology | CMOS EPROM | CMOS, UV-erasable |
| Package Code | QCCJ | QCCJ |
| Package Type | 68-pin JLCC (J-leaded ceramic chip carrier) | — |
| Terminal Form | J BEND | — |
| Package Shape | SQUARE | — |
| Number of Terminals | 68 | — |
| Temperature Grade | INDUSTRIAL | Commercial |
| 工作温度 | -40 °C to +85 °C | — |
| 电源电压 | 5 V (TTL compatible) | — |
| Programming Method | UV-erase (windowed) / OTP via JEDEC | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP1810 (Classic EPLD Family) |
| Macrocells | — | 48 |
| Equivalent Gates | — | 2100 gates |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| Propagation Delay (tpd) | — | 45 ns |
| 最大时钟频率 | — | 33.3 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| 封装 | — | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| 引脚数量 | — | 68 |
| 安装类型 | — | Surface Mount |
| RoHS 状态 | — | [DATA_NEEDED: RoHS compliance not stated in verified data] |