EP1810LC-35 vs EP1810LC-20 对比
详细并排对比 EP1810LC-35 出自 Rochester Electronics 和 EP1810LC-20 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Rochester Electronics
EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
EP1810LC-35 ⚠ 最后一次采购规格对比
| 参数 | EP1810LC-35 | EP1810LC-20 |
|---|---|---|
| 品牌 | Rochester Electronics | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 最后采购期 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $49.20 | $7.85 |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Series | Classic EP1810 | — |
| Macrocells | 48 | 48 |
| Equivalent Gates | 900 usable / 2100 equivalent | — |
| Maximum Operating Frequency | 28.6 MHz | 50 MHz |
| Propagation Delay (tpd) | 35 ns (max, '-35' speed grade) | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS, UV-erasable EPROM | CMOS EPROM |
| 封装 | 68-pin PLCC (J-Lead) | 68-pin PLCC |
| 安装类型 | Surface Mount (socketable) | Surface Mount |
| 工作温度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| I/O Pins | [DATA_NEEDED: I/O count exact] | — |
| Configuration Method | UV-erase + EPROM programmer | — |
| Programmable Interconnect | Centralized Programmable Interconnect Array (PIA) | — |
| Development Tool (legacy) | MAX+PLUS II / A+PLUS | — |
| RoHS 状态 | [DATA_NEEDED] | [DATA_NEEDED: rohs status] |
| Lead-Free | [DATA_NEEDED] | — |
| Family | — | Classic EPLD |
| Usable Gates | — | 900 |
| Propagation Delay (tPD) | — | 20 ns |
| 电源电压 | — | 5 V (4.75 V to 5.25 V) |
| Programmability | — | UV-Erasable / OTP |
| Dedicated Inputs | — | 12 |
| Package Suffix | — | LC (PLCC, windowed for UV erase on L variant) |
| Speed Grade | — | 20 ns (commercial) |