EP1810LC-35T vs EP1810LC-20T 对比
详细并排对比 EP1810LC-35T 出自 Intel 和 EP1810LC-20T 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1810LC-35T | EP1810LC-20T |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $115.20 | $9.95 |
| Device Family | EP1810 Classic EPLD | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 900 | 900 gates |
| Macro Cells | 48 | — |
| Pin-to-Pin Delay (tpd) | 35 ns | — |
| Maximum Frequency (fmax) | 28.6 MHz | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS | — |
| Logic Compatibility | 100% TTL emulation | — |
| 封装 | 68-pin PLCC (Plastic Leaded Chip Carrier) | — |
| Package Suffix | T = Tape and Reel | — |
| 工作温度 | 0 C to +70 C (Commercial) | 0C to +70C (commercial) |
| 安装类型 | Surface Mount (PLCC socket or direct solder) | Surface Mount (socket-compatible) |
| Programming Method | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II | — |
| RoHS 状态 | Non-compliant (legacy PLCC product) | Non-compliant (legacy 5V PLCC) |
| Logic Family Replacement Target | 74LS low-power Schottky TTL | — |
| Family | — | Altera Classic EPLD |
| Macrocells | — | 48 |
| Logic Array Blocks (LABs) | — | 4 x 12 macrocells |
| Maximum Toggle Frequency | — | 50 MHz |
| Pin-to-Pin Logic Delay (tPD) | — | 20 ns |
| Supply Voltage (VCC) | — | 5 V |
| Package Type | — | PLCC-68 (J-lead) |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |
| Programming Interface | — | JTAG (IEEE 1149.1) and Altera Master/Slave serial |
| Shipping Format | — | Tape & Reel ("T" suffix) |