EP1C20F400C7N vs EP1C20F400 对比
详细并排对比 EP1C20F400C7N 出自 Altera 和 EP1C20F400 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1C20F400C7N | EP1C20F400 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $65.80 | $58.90 |
| Series | Cyclone | — |
| Family | Cyclone I | Cyclone |
| Logic Elements (LE) | 20,060 | — |
| Logic Array Blocks (LABs) | 2,006 | — |
| Embedded Memory (bits) | 294,912 (288 Kbits, M4K blocks) | — |
| User I/O Count | 301 | — |
| Embedded 18x18 Multipliers | 52 | — |
| PLLs | 4 | — |
| Process Technology | 130 nm CMOS (SRAM-based) | 0.13 µm SRAM |
| Core Voltage | 1.5 V | — |
| Speed Grade | -7 (commercial, ~405 MHz internal) | — |
| 工作温度 | 0 °C to +85 °C (commercial) | — |
| 封装 | 400-ball FineLine BGA (FBGA) | 400-ball FineLine BGA (F400) |
| 安装类型 | Surface Mount | Surface Mount (BGA) |
| Configuration Interface | Active Serial (AS) / Passive Serial (PS) / JTAG | — |
| I/O Standards Supported | LVTTL, LVCMOS, SSTL, HSTL, LVDS (via 8 I/O banks) | — |
| External Memory Support | DDR SDRAM, QDR SRAM, FCRAM | — |
| RoHS 状态 | Compliant (per Altera product page) | [DATA_NEEDED: RoHS status] |
| Manufacturer | — | Altera (now Intel) |
| Logic Elements (LEs) | — | 20,060 |
| Embedded RAM Bits | — | 294,912 bits |
| M4K RAM Blocks (4 Kbit + parity) | — | 301 |
| Embedded 18×18 Multipliers | — | 20 |
| Phase-Locked Loops (PLLs) | — | 8 |
| Maximum User I/O Pins | — | 301 |
| Core Voltage (VCCINT) | — | 1.5 V (typical) |
| I/O Bank Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) |
| LVDS Data Rate | — | up to 840 Mbps |
| Single-Ended I/O Standard Support | — | LVTTL, LVCMOS, PCI, SSTL, LVDS |
| Configuration Modes | — | Passive Serial (PS), Active Serial (AS), JTAG |
| 工作结温 | — | -40 °C to +100 °C (commercial/industrial grades) |