EP1K100QC208-3N vs EP1K100QC208-3 对比

详细并排对比 EP1K100QC208-3N 出自 Altera 和 EP1K100QC208-3 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EP1K100QC208-3N EP1K100QC208-3N - ACEX-1K FPGA 100K Gates | Altera

EP1K100QC208-3N - ACEX-1K FPGA 100K Gates | Altera

EP1K100QC208-3N Obsolete

规格对比

参数 EP1K100QC208-3N EP1K100QC208-3
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $19.50 $60.04
Product Series ACEX-1K —
Device Type Field Programmable Gate Array (FPGA) FPGA (Field Programmable Gate Array)
Number of Logic Elements 4992 4,992
Number of LABs 624 —
Embedded RAM Bits 49152 —
Total Typical Gates 100K —
Number of User I/Os 147 —
Core Supply Voltage 2.5 V 2.5 V
I/O Supply Voltage Range [DATA_NEEDED: I/O supply voltage range] —
Maximum Internal Clock Frequency 200 MHz 200 MHz
Package Type 208-BFQFP 208-Pin BFQFP (PQFP)
引脚数 208 —
安装类型 Surface Mount Surface Mount
Terminal Form Gull Wing Gull Wing
JTAG Boundary Scan IEEE Std. 1149.1-1990 compliant built-in BST —
Lead-Free Version Yes (N suffix) —
工作温度范围 Commercial grade ([DATA_NEEDED: exact operating temperature range]) —
Supported Configuration Devices EPC2/EPC16 family ([DATA_NEEDED: exact ACEX-1K supported list]) —
Moisture Sensitivity Level [DATA_NEEDED: MSL level] —
RoHS 状态 [DATA_NEEDED: RoHS certificate status] —
Product Family — ACEX 1K
Process Technology — 0.22 um CMOS
Typical Gate Count — 100,000 gates
Logic Array Blocks (LABs) — 624
Total RAM Bits — 49,152 bits
Maximum User I/O — 147
Number of Terminals — 208
Package Shape — Square
Temperature Grade — Commercial
Speed Grade — -3
RoHS / Lead-Free Suffix — No -N suffix; compliance not verified in retrieved source data
I/O Standards Supported — [DATA_NEEDED: supported I/O standards]
Configuration Memory — SRAM-based loadable PLD

数据手册与资源

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