EP1K10TC100-2N vs EP1K10TC100-3N 对比

详细并排对比 EP1K10TC100-2N 出自 Altera 和 EP1K10TC100-3N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EP1K10TC100-2N EP1K10TC100-2N - ACEX-1K FPGA, 10K Gates, 576 Cells | Altera

EP1K10TC100-2N - ACEX-1K FPGA, 10K Gates, 576 Cells | Altera

EP1K10TC100-2N ⚠ 最后一次采购

规格对比

参数 EP1K10TC100-2N EP1K10TC100-3N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $8.25 $19.95
Family ACEX-1K ACEX 1K
Logic Elements / Cells 576 —
Typical Gates 10,000 —
Logic Array Blocks (LABs) 72 —
Embedded Memory (EAB) 12,288 bits 12,288 bits
Maximum User I/O 66 —
Process Technology 0.22 um CMOS 0.22 µm CMOS
Core Voltage (VCCINT) 2.5 V —
I/O Voltage (VCCIO) 1.8 V / 2.5 V / 3.3 V / 5 V —
Speed Grade -2 -3 (commercial)
Maximum Frequency 200 MHz —
封装 100-pin TQFP (1.0 mm body, 0.5 mm pitch) 100-pin TQFP
工作温度 0 C to +70 C (commercial) [DATA_NEEDED: operating temperature range]
Configuration Modes Passive Serial, Active Serial, JTAG —
安装类型 Surface Mount —
RoHS 状态 Lead-free / RoHS compliant [DATA_NEEDED: RoHS compliance]
Series — ACEX-1K
Manufacturer — Intel (formerly Altera)
Typical Gate Count — 10,000 gates
Logic Elements (Cells) — 576
Number of LABs — 72
User I/O Count — 66
Operating Voltage (Core) — 2.5 V
Maximum Internal Clock Frequency — 200 MHz
JTAG Support — Yes (IEEE 1149.1-1990)
PCI Compliance — PCI Local Bus Specification Revision 2.2 (5.0 V)
Configuration — JTAG / serial configuration device

数据手册与资源

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