EP1K10TC100-3N vs EP1K10TC100-2N 对比
详细并排对比 EP1K10TC100-3N 出自 Intel 和 EP1K10TC100-2N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Intel
EP1K10TC100-3N - 10K-Gate ACEX-1K FPGA, 576 Cells, 66 I/O, 100-TQFP | Intel / Altera
EP1K10TC100-3N Obsolete规格对比
| 参数 | EP1K10TC100-3N | EP1K10TC100-2N |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $19.95 | $8.25 |
| Series | ACEX-1K | — |
| Family | ACEX 1K | ACEX-1K |
| Manufacturer | Intel (formerly Altera) | — |
| Typical Gate Count | 10,000 gates | — |
| Logic Elements (Cells) | 576 | — |
| Embedded Memory (EAB) | 12,288 bits | 12,288 bits |
| Number of LABs | 72 | — |
| User I/O Count | 66 | — |
| Operating Voltage (Core) | 2.5 V | — |
| Process Technology | 0.22 µm CMOS | 0.22 um CMOS |
| Maximum Internal Clock Frequency | 200 MHz | — |
| Speed Grade | -3 (commercial) | -2 |
| 封装 | 100-pin TQFP | 100-pin TQFP (1.0 mm body, 0.5 mm pitch) |
| JTAG Support | Yes (IEEE 1149.1-1990) | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 (5.0 V) | — |
| Configuration | JTAG / serial configuration device | — |
| 工作温度 | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (commercial) |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance] | Lead-free / RoHS compliant |
| Logic Elements / Cells | — | 576 |
| Typical Gates | — | 10,000 |
| Logic Array Blocks (LABs) | — | 72 |
| Maximum User I/O | — | 66 |
| Core Voltage (VCCINT) | — | 2.5 V |
| I/O Voltage (VCCIO) | — | 1.8 V / 2.5 V / 3.3 V / 5 V |
| Maximum Frequency | — | 200 MHz |
| Configuration Modes | — | Passive Serial, Active Serial, JTAG |
| 安装类型 | — | Surface Mount |