EP1K30TC144-3 vs EP1K30TC144-1N 对比
详细并排对比 EP1K30TC144-3 出自 Intel 和 EP1K30TC144-1N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1K30TC144-3 | EP1K30TC144-1N |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $10.80 | $11.50 |
| Series | ACEX-1K | ACEX-1K |
| Logic Elements / Cells | 1,728 | — |
| Total RAM Bits | 24,576 | — |
| Number of LABs/CLBs | 216 | — |
| Typical Gates | 30,000 | 30,000 |
| Maximum System Gates | 56,000 | — |
| Number of User I/O | 102 | 102 |
| Number of Logic Array Blocks | 216 | — |
| Supply Voltage (Core) | 2.5 V | — |
| I/O Voltage Standard | 2.5 V LVCMOS / LVTTL (MultiVolt up to 5.0 V tolerant) | — |
| Process Technology | 0.22 µm SRAM | 0.18 µm SRAM |
| Operating Temperature (Commercial) | 0C to +70C | — |
| 封装 | 144-LQFP / 144-TQFP (22x22 mm, 0.5 mm pitch) | — |
| 安装类型 | Surface Mount | Surface Mount |
| Speed Grade | -3 (slowest speed bin) | — |
| Configuration Method | Serial configuration device (EPC2/EPC8 compatible) | — |
| Boundary Scan | IEEE 1149.1 JTAG compliant | — |
| Number of Global Clocks | 8 | — |
| RoHS 状态 | [DATA_NEEDED: rohs status from datasheet] | [DATA_NEEDED: RoHS compliance status] |
| Number of Logic Elements (LEs) | — | 1,728 |
| Number of Logic Array Blocks (LABs) | — | 216 |
| Embedded Memory (EAB) | — | 24,576 bits (6 EABs) |
| Number of I/O Banks | — | 4 |
| Package Type | — | 144-LQFP (TQFP) |
| Core Voltage | — | 2.5 V |
| I/O Voltage | — | 3.3 V (LVCMOS/LVTTL); 2.5 V tolerant |
| 工作温度 | — | [DATA_NEEDED: operating temperature range] |
| Configuration | — | SRAM-based, JTAG (IEEE 1149.1) + serial/parallel passive |
| PLLs | — | 6 (per device family) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| MSL 等级 | — | [DATA_NEEDED: MSL moisture sensitivity level] |