EP1K30TI144-3N vs EP1K30TI144-2NGA 对比
详细并排对比 EP1K30TI144-3N 出自 Altera 和 EP1K30TI144-2NGA 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1K30TI144-3N | EP1K30TI144-2NGA |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $21.80 | $18.20 |
| Family | ACEX 1K | — |
| Series | EP1K30 | ACEX 1K |
| Logic Elements | 1,728 | — |
| Typical Gates | 30,000 | — |
| Usable Gates | 17,500 | — |
| Embedded Memory (EAB) | 24 Kbit (6 EABs of 4 Kbit each) | — |
| Maximum User I/O Pins | 102 | — |
| Dedicated Input Pins | 6 | — |
| Total Terminals | 144 | — |
| 封装 | TQFP-144 (0.5 mm pitch) | — |
| Core Supply Voltage | 2.5 V nominal (2.375 V min, 2.625 V max) | — |
| Speed Grade | -3 (fastest in EP1K30 family) | -2 (faster than -3) |
| 工作温度 | -40C to +85C (Industrial) | -40C to +85C (Industrial) |
| Process Technology | 0.18 um CMOS, 4 metal layers | 0.18 um SRAM CMOS |
| Configuration Modes | Passive Serial, Passive Parallel Async, Passive Parallel Sync, JTAG (IEEE 1149.1) | — |
| PLLs | 4 | — |
| 安装类型 | Surface Mount (Gull-Wing) | Surface Mount |
| Thermal Resistance (theta_JA) | Approximately 35-40 C/W (PCB-dependent) | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | — |
| Logic Elements / Cells | — | 1728 |
| Total RAM Bits | — | 24576 |
| Number of Logic Array Blocks (LABs) | — | 216 |
| Number of I/O | — | 102 |
| Number of Gates (typical) | — | 119000 |
| Core Voltage (VCCINT) | — | 2.5 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V |
| 封装 / 外壳 | — | 144-LFQFP / 144-TQFP (20x20 mm) |
| Programmable Logic Type | — | In-system programmable SRAM FPGA |
| Lead Free / RoHS Status | — | Lead free / RoHS compliant per suffix code |
| Design Software | — | Quartus II, MAX+PLUS II |
| JTAG Support | — | Yes (IEEE 1149.1 boundary scan) |
| Configuration | — | SRAM-based, requires configuration device at power-up |