EP1K50QC208-1N vs EP1K50QC208-2N 对比

详细并排对比 EP1K50QC208-1N 出自 Altera 和 EP1K50QC208-2N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EP1K50QC208-1N EP1K50QC208-1N - ACEX 1K FPGA, 2880 LE, 250MHz | Altera

EP1K50QC208-1N - ACEX 1K FPGA, 2880 LE, 250MHz | Altera

EP1K50QC208-1N ✓ 量产中

规格对比

参数 EP1K50QC208-1N EP1K50QC208-2N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 Obsolete
库存状态 有库存 有库存
单价(USD) $0.00 $27.80
Product Type Field Programmable Gate Array (FPGA) —
Family ACEX 1K ACEX 1K
Number of Logic Elements 2880 LE —
Number of LABs 360 LABs —
Embedded Memory Bits 40960 bits (40 kbit) —
Embedded RAM Capability RAM, ROM, dual-port RAM, FIFO (per ACEX 1K architecture) —
Maximum User I/O 147 I/O —
Typical Gate Count 50000 gates —
Core Supply Voltage 2.5 V 2.5 V
Maximum Operating Frequency 250 MHz —
Speed Grade -1 —
Process Technology 0.22 um CMOS 0.22 µm CMOS
Package Type 208-BFQFP (PQFP-208) —
Terminal Form Gull wing —
Package Shape Square —
安装类型 Surface Mount Surface Mount (Gull-Wing)
Lead-Free Finish N suffix, lead-free finish per Altera part numbering —
工作温度范围 [DATA_NEEDED: exact operating temperature range] —
Series — ACEX-1K
Logic Elements — 2,880
Typical Gates — 50,000
Logic Array Blocks (LABs) — 360
Embedded Memory (EAB SRAM) — 40 kbit
User I/Os — 147
Number of I/O Banks — [DATA_NEEDED: number of I/O banks]
Maximum Toggle Frequency — 200 MHz
Pin-to-Pin Delay (LE) — 0.4 ns (per data sheet snippet)
I/O Supply Voltage — [DATA_NEEDED: I/O supply voltage]
Configuration Interface — JTAG (IEEE 1149.1), Serial (PS/AS)
封装 — 208-pin PQFP (BFQFP)
工作温度 — 0 °C to 85 °C (Commercial)
MSL 等级 — [DATA_NEEDED: MSL level]
RoHS 状态 — [DATA_NEEDED: RoHS status]

数据手册与资源

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