EP1K50QC208-2N vs EP1K50QC208-3 对比

详细并排对比 EP1K50QC208-2N 出自 Intel 和 EP1K50QC208-3 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1K50QC208-2N EP1K50QC208-3
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $27.80 $12.10
Series ACEX-1K —
Family ACEX 1K ACEX 1K
Logic Elements 2,880 —
Typical Gates 50,000 50,000
Logic Array Blocks (LABs) 360 360
Embedded Memory (EAB SRAM) 40 kbit —
User I/Os 147 —
Number of I/O Banks [DATA_NEEDED: number of I/O banks] —
Maximum Toggle Frequency 200 MHz —
Pin-to-Pin Delay (LE) 0.4 ns (per data sheet snippet) —
Process Technology 0.22 µm CMOS 0.22 µm CMOS
Core Supply Voltage 2.5 V 2.5 V
I/O Supply Voltage [DATA_NEEDED: I/O supply voltage] —
Configuration Interface JTAG (IEEE 1149.1), Serial (PS/AS) —
封装 208-pin PQFP (BFQFP) 208-pin PQFP (BFQFP)
安装类型 Surface Mount (Gull-Wing) Surface Mount
工作温度 0 °C to 85 °C (Commercial) Commercial (0°C to +70°C) [DATA_NEEDED: exact range]
MSL 等级 [DATA_NEEDED: MSL level] —
RoHS 状态 [DATA_NEEDED: RoHS status] unknown
Logic Elements / Cells — 2,880
RAM Bits — 40,960
Embedded Array Blocks (EABs) — 12
User I/O Pins — 147
Maximum Operating Frequency — 166.67 MHz
Speed Grade — -3
Configuration Mode — Passive Serial, Active Serial, JTAG
I/O Standards — LVTTL, LVCMOS, PCI
Design Tool Support — Quartus II, MAX+PLUS II

数据手册与资源

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