EP1K50QC208-3N vs EP1K50QC208-2N 对比

详细并排对比 EP1K50QC208-3N 出自 Altera 和 EP1K50QC208-2N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1K50QC208-3N EP1K50QC208-2N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $13.85 $27.80
Family ACEX-1K ACEX 1K
Typical Gates 50,000 50,000
Logic Elements (LEs) 2,880 —
Logic Array Blocks (LABs) 360 360
Embedded RAM 40,960 bits (10 EABs × 4,096 bits) —
Maximum User I/Os 147 —
Maximum Operating Frequency 166.67 MHz —
Pin-to-Pin Logic Delay 0.5 ns (typical, -3 speed grade) —
Process Technology 0.22 µm CMOS 0.22 µm CMOS
Core Supply Voltage (VCCINT) 2.5 V —
I/O Supply Voltage (VCCIO) 3.3 V (PCI-compatible I/O banks) —
封装 208-pin PQFP / BFQFP (Plastic Quad Flat Pack) 208-pin PQFP (BFQFP)
安装类型 Surface Mount Surface Mount (Gull-Wing)
工作温度 0 °C to +70 °C (Commercial) 0 °C to 85 °C (Commercial)
Programming Interface IEEE 1149.1 JTAG + in-system configurable —
Lead-Free / RoHS Compliant (Pb-free terminal finish per 'N' suffix) —
Series — ACEX-1K
Logic Elements — 2,880
Embedded Memory (EAB SRAM) — 40 kbit
User I/Os — 147
Number of I/O Banks — [DATA_NEEDED: number of I/O banks]
Maximum Toggle Frequency — 200 MHz
Pin-to-Pin Delay (LE) — 0.4 ns (per data sheet snippet)
Core Supply Voltage — 2.5 V
I/O Supply Voltage — [DATA_NEEDED: I/O supply voltage]
Configuration Interface — JTAG (IEEE 1149.1), Serial (PS/AS)
MSL 等级 — [DATA_NEEDED: MSL level]
RoHS 状态 — [DATA_NEEDED: RoHS status]

数据手册与资源

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