EP1K50TC144-1 vs EP1K30TC144-1N 对比

详细并排对比 EP1K50TC144-1 出自 Altera 和 EP1K30TC144-1N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1K50TC144-1 EP1K30TC144-1N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $9.95 $11.50
Family ACEX-1K —
Logic Elements / Cells 2,880 —
System Gates 50,000 —
Embedded Memory (Bits) 40,960 —
Logic Array Blocks (LABs) 360 —
User I/O Pins 102 —
Core Voltage 2.5 V 2.5 V
I/O Voltage 2.5 V (5-V tolerant I/O) 3.3 V (LVCMOS/LVTTL); 2.5 V tolerant
Maximum Internal Frequency 250 MHz —
Process Technology CMOS 0.18 µm SRAM
Embedded Array Blocks (EABs) Dual-port, configurable as RAM/ROM —
封装 144-pin LQFP (TQFP) —
安装类型 Surface Mount (Gull-Wing Leads) Surface Mount
Operating Temperature Grade Commercial —
Programming Interface JTAG (IEEE 1149.1) + serial configuration —
Development Tools MAX+PLUS II, Quartus —
Lead-Free / RoHS [DATA_NEEDED: Lead-free / RoHS status] —
MSL 等级 [DATA_NEEDED: MSL moisture sensitivity level] [DATA_NEEDED: MSL moisture sensitivity level]
Series — ACEX-1K
Number of Logic Elements (LEs) — 1,728
Typical Gates — 30,000
Number of Logic Array Blocks (LABs) — 216
Embedded Memory (EAB) — 24,576 bits (6 EABs)
Number of User I/O — 102
Number of I/O Banks — 4
Package Type — 144-LQFP (TQFP)
工作温度 — [DATA_NEEDED: operating temperature range]
Configuration — SRAM-based, JTAG (IEEE 1149.1) + serial/parallel passive
PLLs — 6 (per device family)
RoHS 状态 — [DATA_NEEDED: RoHS compliance status]
Lead-Free — [DATA_NEEDED: lead-free status]

数据手册与资源

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