EP1K50TC144-3N vs EP1K50TI144-2N 对比

详细并排对比 EP1K50TC144-3N 出自 Intel 和 EP1K50TI144-2N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1K50TC144-3N EP1K50TI144-2N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $9.15 $9.95
Series ACEX-1K —
Family ACEX 1K Programmable Logic Device Family ACEX-1K
Logic Elements / Cells 2880 —
System Gates 40960 (50K nominal) —
Number of LABs/CLBs 360 —
Embedded Memory (EAB) 40 kbit (12 EABs, dual-port) —
User I/O Count 102 102
Number of Gates 199000 (maximum) —
Operating Frequency (Max) 166.67 MHz —
Core Voltage 2.5 V —
I/O Voltage Support 2.5 V / 3.3 V / 5.0 V (multiVolt) —
Process Technology 0.22 µm CMOS 0.22 µm
Logic Delay (pin-to-pin) 5.0 ns —
封装 144-LQFP (TQFP-144), 22 x 22 mm, 0.5 mm pitch 144-LQFP (TQFP, 0.5 mm pitch)
Programming Interface JTAG (IEEE 1149.1) / Altera serial —
Operating Temperature Grade Commercial (0 °C to +70 °C) — inferred from '-N' suffix —
安装类型 Surface Mount Surface Mount
RoHS 状态 Compliant —
Logic Elements — 40,960
Typical Gates — 50,000
Logic Cells — 2,880
Logic Array Blocks (LABs) — 360
Maximum Operating Frequency — 166.67 MHz
Embedded RAM Bits — 40,960 (12 ESBs)
Operating Voltage (VCCINT) — 2.5 V
工作温度 — -40C to +85C (industrial, "N" suffix)
Speed Grade — -2 (faster)
Configuration Method — SRAM / JTAG (IEEE 1149.1)
Lead-Free / RoHS — Check supplier (ACEX-1K predates RoHS mandate)

数据手册与资源

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