EP1K50TI144-3N vs EP1K50TI144-4N 对比

详细并排对比 EP1K50TI144-3N 出自 Altera 和 EP1K50TI144-4N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1K50TI144-3N EP1K50TI144-4N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $19.80 $9.85
Family ACEX 1K (EP1K) ACEX 1K
Series EP1K50 —
Logic Elements 2,880 —
Typical Gates 50,000 50,000
Embedded Array Blocks (EABs) 40 (4 Kbit each) 10 (12.6 Kbit total)
Embedded Memory (EAB SRAM) 40,960 bits —
Maximum User I/O 102 —
Dedicated Inputs 6 —
Core Voltage (VCCINT) 2.375 V to 2.625 V (nominal 2.5 V) —
I/O Bank Voltage (VCCIO) 2.375 V to 5.0 V (multiVolt I/O) —
Speed Grade -3 (fastest ACEX 1K grade) -4
Maximum Internal Frequency 166.67 MHz (process node data) —
Process Technology 0.22 µm CMOS, SRAM-based 0.18 µm CMOS SRAM-based
封装 144-pin TQFP (Industrial, Pb-free) 144-pin TQFP (TQFP-144), 0.5 mm pitch
工作温度 -40 °C to +85 °C (Industrial) —
安装类型 Surface Mount Surface Mount
Configuration Interface JTAG (IEEE 1149.1) + passive-serial —
RoHS 状态 Compliant (Pb-free terminal finish, "N" suffix) [DATA_NEEDED: RoHS status - not stated in provided data]
MSL 等级 [DATA_NEEDED: MSL level] —
Supply Current (typ/ICC) [DATA_NEEDED: ICC standby] —
Device Type — Field-Programmable Gate Array (FPGA)
Maximum Usable Gates — 40,960
Logic Elements (LEs) — 2,880
Maximum User I/O Pins — 102
Dedicated Input Pins — 6
Supply Voltage (VCCINT) — 2.375 V to 2.625 V (nominal 2.5 V)
I/O Bank Supply Voltages — 2.5 V / 3.3 V / 5.0 V compatible (MultiVolt I/O)
Configuration Method — Serial configuration EPROM (EPC2/EPC8) or JTAG
Operating Temperature (Industrial 'N' suffix) — -40 °C to +85 °C
Lead-Free — [DATA_NEEDED: lead-free status]

数据手册与资源

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