EP1M120F480C6 vs EP1M120B484C6 对比

详细并排对比 EP1M120F480C6 出自 Altera 和 EP1M120B484C6 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1M120F480C6 EP1M120B484C6
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $99.50 $55.00
Family Mercury PLD (FPGA) Mercury (ACEX 1M)
Logic Elements 49,152 (typical) —
Total RAM Bits [DATA_NEEDED: total embedded memory bits] —
User I/O Count 303 (max) —
封装 480-ball FineLine BGA 484-ball FineLine BGA (BGA-484)
工作温度 0C to +85C (commercial, C grade) —
Speed Grade -6 —
Core Voltage 1.5 V —
Process Technology 0.18 micron CMOS SRAM —
Transceivers 8 channels at 1.25 Gbps + 10 channels up to 1.0 Gbps —
Configuration SRAM-based, requires external configuration device —
安装类型 Surface Mount (BGA) Surface Mount
MSL 等级 [DATA_NEEDED: moisture sensitivity level] —
RoHS 状态 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Programmable Logic Type Field Programmable Gate Array (FPGA) —
Number of Gates 120,000 (max, marketing nomenclature) —
Logic Elements (typical) — 120 LE
Maximum Logic Elements — [DATA_NEEDED: maximum logic elements]
Flip-Flops — 4,800
User I/O Pins (max) — 303
Configuration Memory — SRAM-based (volatile, re-load on power-up)
Peak Reflow Temperature — 220 °C
Operating Temperature Grade — Commercial (C suffix)
Process Node — 0.18 µm
JTAG Support — IEEE 1149.1 boundary-scan
Configuration Modes — PS, AS, JTAG
Design Software — Quartus II (legacy support required)

数据手册与资源

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