EP1M120F484C8N vs EP1M120F484I6M 对比

详细并排对比 EP1M120F484C8N 出自 Altera 和 EP1M120F484I6M 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1M120F484C8N EP1M120F484I6M
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $142.00 $325.00
Family Mercury (EP1M) Mercury (EP1M)
Logic Family CMOS, SRAM-based —
Number of Logic Elements 49,152 —
Embedded Memory 4,800 Kbits (M4K blocks) —
User I/O Pins 303 —
Package Type FINE LINE BGA-484 484-Ball FCBGA
Terminal Pitch 1.000 mm —
安装类型 Surface Mount —
Supply Voltage (Core) 1.8 V nominal (1.71 V min, 1.89 V max) —
Speed Grade 8 -6 (slowest Mercury timing bin)
工作温度 0 °C to 85 °C (Commercial) —
Transceivers Up to 8 channels with CDR up to 1.25 Gbps —
Configuration SRAM, JTAG via Quartus II —
RoHS 状态 [DATA_NEEDED: RoHS compliance] Compliant (M revision)
MSL 等级 [DATA_NEEDED: MSL rating] —
Logic Elements — 120,000
System Gates — 480,000 (typical)
LABs / CLBs — 303
Flip-Flops — 49,152
Embedded Memory (Bits) — 4,800 Kb (480 Kbits)
Package Code — BGA, 484 balls, Fine-pitch
Package Shape — Square
Terminal Form — Ball
Temperature Grade — Industrial
电源电压 — 1.5 V core / 3.3 V aux (per Mercury datasheet)
I/O Standards — LVTTL, LVCMOS, SSTL, HSTL, LVDS
Clock Management — PLLs (per Mercury family)
Boundary-Scan — IEEE 1149.1 / JTAG

数据手册与资源

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