EP1M120F484I6M vs EP1M120F484I6 对比
详细并排对比 EP1M120F484I6M 出自 Altera 和 EP1M120F484I6 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1M120F484I6M | EP1M120F484I6 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $325.00 | $95.00 |
| Family | Mercury (EP1M) | Altera / Intel Mercury programmable logic device (PLD) |
| Logic Elements | 120,000 | 49,152 |
| System Gates | 480,000 (typical) | — |
| LABs / CLBs | 303 | — |
| Flip-Flops | 49,152 | — |
| Embedded Memory (Bits) | 4,800 Kb (480 Kbits) | — |
| Package Type | 484-Ball FCBGA | 484-BBGA, FCBGA (FineLine BGA) |
| Package Code | BGA, 484 balls, Fine-pitch | — |
| Package Shape | Square | — |
| Terminal Form | Ball | — |
| Temperature Grade | Industrial | — |
| Speed Grade | -6 (slowest Mercury timing bin) | -6 |
| 电源电压 | 1.5 V core / 3.3 V aux (per Mercury datasheet) | — |
| I/O Standards | LVTTL, LVCMOS, SSTL, HSTL, LVDS | — |
| Clock Management | PLLs (per Mercury family) | — |
| Boundary-Scan | IEEE 1149.1 / JTAG | — |
| RoHS 状态 | Compliant (M revision) | [DATA_NEEDED: RoHS status not specified in verified data] |
| Series | — | Mercury (EP1M) |
| Memory Bits | — | 4,800 (480 Kbits) |
| Number of LABs/CLBs | — | 480 |
| User I/Os | — | 303 |
| Number of Gates | — | [DATA_NEEDED: nominal gate count] |
| Core Supply Voltage | — | 1.8 V |
| 工作温度 | — | 0C to +85C (Industrial) |
| Pins / Balls | — | 484 |
| Logic Family | — | CMOS |
| High-Speed Transceivers | — | Integrated CDR-based, up to 1.25 Gbps |
| Transceiver Channels (1.25 Gbps) | — | Up to 4 channels on EP1M120 (EP1M350 up to 8) |
| Design Tool | — | Altera Quartus II |
| 安装类型 | — | Surface Mount (BGA) |