EP1S10B672C6 vs EP1S10B672C7N 对比
详细并排对比 EP1S10B672C6 出自 Intel 和 EP1S10B672C7N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1S10B672C6 | EP1S10B672C7N |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $185.00 | $67.90 |
| Manufacturer | Intel / Altera | Intel / Altera |
| Series | Stratix | — |
| Logic Elements / Cells | 10,570 | — |
| LABs / CLBs | 1,057 | — |
| User I/Os | 345 | — |
| 封装 | 672-BBGA (35 x 35 mm, 1.27 mm pitch) | — |
| Supply Voltage (Core) | 1.5 V (1.425 V - 1.575 V) | — |
| Process Technology | 130 nm CMOS | — |
| Maximum Operating Frequency | 450.05 MHz | — |
| 工作温度 | 0 C to 85 C (Commercial Extended) | — |
| Logic Family | CMOS | CMOS |
| 安装类型 | Surface Mount (BGA) | — |
| Supplier Device Package | 672-BGA | — |
| Memory | Embedded TriMatrix (MRAM/M4K) blocks | — |
| DSP Blocks | Yes, dedicated multiply-accumulate blocks | — |
| Clock Management | PLLs for clock synthesis | — |
| Configuration | JTAG / passive serial / fast passive parallel | — |
| RoHS 状态 | Compliant | — |
| Product Family | — | Stratix |
| Logic Elements/Cells | — | 10570 cells |
| Maximum Internal Clock | — | 420.17 MHz |
| Core Supply Voltage | — | 1.5 V |
| Technology Node | — | 130 nm |
| Package Code | — | BGA |
| Number of Terminals | — | 672 |
| Package Body Size | — | 35 x 35 mm |
| Ball Pitch | — | 1.27 mm |
| Package Shape | — | Square |
| Temperature Grade | — | Commercial extended, 0 to 85 C |
| Terminal Form | — | Ball |
| Configuration/JTAG | — | JTAG boundary-scan per Stratix family data sheet |
| Number of User I/O in 672-BGA | — | [DATA_NEEDED: user I/O count] |
| Total RAM Bits | — | [DATA_NEEDED: total RAM bits] |
| Embedded PLLs | — | [DATA_NEEDED: PLL count] |
| Config Device Compatibility | — | [DATA_NEEDED: supported configuration devices] |
| RoHS | — | unknown - N suffix may indicate Pb-free, not verified in fetched data |