EP1S10B672C6 vs EP1S10F672C6 对比
详细并排对比 EP1S10B672C6 出自 Intel 和 EP1S10F672C6 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1S10B672C6 | EP1S10F672C6 |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $185.00 | $72.00 |
| Manufacturer | Intel / Altera | — |
| Series | Stratix | Stratix® I |
| Logic Elements / Cells | 10,570 | — |
| LABs / CLBs | 1,057 | — |
| User I/Os | 345 | — |
| 封装 | 672-BBGA (35 x 35 mm, 1.27 mm pitch) | 672-ball FineLine BGA (FBGA) |
| Supply Voltage (Core) | 1.5 V (1.425 V - 1.575 V) | — |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Maximum Operating Frequency | 450.05 MHz | — |
| 工作温度 | 0 C to 85 C (Commercial Extended) | 0C to +85C (Commercial) |
| Logic Family | CMOS | — |
| 安装类型 | Surface Mount (BGA) | Surface Mount (BGA) |
| Supplier Device Package | 672-BGA | — |
| Memory | Embedded TriMatrix (MRAM/M4K) blocks | — |
| DSP Blocks | Yes, dedicated multiply-accumulate blocks | 6 |
| Clock Management | PLLs for clock synthesis | — |
| Configuration | JTAG / passive serial / fast passive parallel | — |
| RoHS 状态 | Compliant | [DATA_NEEDED: RoHS status] |
| Family | — | Stratix FPGA |
| Logic Elements (LE) | — | 10,570 |
| Logic Array Blocks (LABs) | — | 1057 |
| Total Memory Bits | — | 920,448 bits |
| Embedded Memory | — | TriMatrix (MRAM/M4K) |
| Number of I/Os | — | 345 |
| Number of PLLs | — | 12 (6 per device side) |
| Core Voltage | — | 1.5 V |
| Maximum Core Frequency | — | 420.17 MHz |
| Configuration Modes | — | Passive Serial (PS), Fast Passive Parallel (FPP), Active Serial (AS) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |