EP1S10B672C7N vs EP1S10F484C5N 对比

详细并排对比 EP1S10B672C7N 出自 Intel 和 EP1S10F484C5N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1S10B672C7N EP1S10F484C5N
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $67.90 $52.00
Manufacturer Intel / Altera —
Product Family Stratix —
Logic Family CMOS —
Logic Elements/Cells 10570 cells —
Maximum Internal Clock 420.17 MHz —
Core Supply Voltage 1.5 V —
Technology Node 130 nm —
Package Code BGA —
Number of Terminals 672 —
Package Body Size 35 x 35 mm —
Ball Pitch 1.27 mm —
Package Shape Square —
Temperature Grade Commercial extended, 0 to 85 C —
Terminal Form Ball —
Configuration/JTAG JTAG boundary-scan per Stratix family data sheet —
Number of User I/O in 672-BGA [DATA_NEEDED: user I/O count] —
Total RAM Bits [DATA_NEEDED: total RAM bits] —
Embedded PLLs [DATA_NEEDED: PLL count] —
Config Device Compatibility [DATA_NEEDED: supported configuration devices] —
RoHS unknown - N suffix may indicate Pb-free, not verified in fetched data —
Series — Stratix
Family — Stratix (original)
Logic Elements (LEs) — 10,570
Logic Array Blocks (LABs) — 1,057
Embedded Memory Bits — 920,448
TriMatrix Memory Blocks — 14
Embedded DSP Blocks — 6 (≈48 9-bit multipliers)
PLLs — 4
Global Clock Networks — 12
Maximum User I/O — 335
User I/O Standard Support — LVDS, LVPECL, PCI-X, RapidIO, DDR
Process Technology — 0.13 µm CMOS
Core Voltage (VCCINT) — 1.5 V
Maximum Internal Frequency — 500 MHz (per Stratix datasheet)
Operating Temperature (TJ) — 0 °C to 85 °C (Commercial)
封装 — 484-ball FCBGA (F484), 23 x 23 mm, 1.0 mm pitch
安装类型 — Surface Mount
Configuration Method — JTAG / Passive Serial / Active Serial
Device Status — Obsolete - last time buy completed
Design Toolchain — Quartus II (≤ v13.0)

数据手册与资源

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