EP1S10F672I7 vs EP1S10B672C7N 对比

详细并排对比 EP1S10F672I7 出自 Intel 和 EP1S10B672C7N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Intel
EP1S10F672I7 EP1S10F672I7 - Stratix FPGA 10K LE, 672-FBGA | Intel

EP1S10F672I7 - Stratix FPGA 10K LE, 672-FBGA | Intel

EP1S10F672I7 ⚠ 最后一次采购

规格对比

参数 EP1S10F672I7 EP1S10B672C7N
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 不推荐新设计
库存状态 有库存 有库存
单价(USD) $124.75 $67.90
Family Stratix —
Logic Elements 10,570 —
User I/O Pins 345 —
封装 FBGA-672, 35 x 35 mm, 1.27 mm pitch —
工作温度 0 C to +85 C (industrial grade, I7) —
Core Supply Voltage 1.5 V 1.5 V
Process Technology 0.13 um CMOS —
Maximum Internal Clock 420.17 MHz (per datasheet) 420.17 MHz
Logic Family CMOS CMOS
Device Type FPGA (Field Programmable Gate Array) —
Total Pins 672 (FBGA) —
Configuration Method JTAG / serial / parallel PROM —
存储器类型 TriMatrix embedded block RAM + distributed RAM —
DSP Blocks Yes (dedicated hardware multipliers) —
安装类型 Surface Mount (BGA) —
RoHS 状态 unknown - verify per lot —
Manufacturer — Intel / Altera
Product Family — Stratix
Logic Elements/Cells — 10570 cells
Technology Node — 130 nm
Package Code — BGA
Number of Terminals — 672
Package Body Size — 35 x 35 mm
Ball Pitch — 1.27 mm
Package Shape — Square
Temperature Grade — Commercial extended, 0 to 85 C
Terminal Form — Ball
Configuration/JTAG — JTAG boundary-scan per Stratix family data sheet
Number of User I/O in 672-BGA — [DATA_NEEDED: user I/O count]
Total RAM Bits — [DATA_NEEDED: total RAM bits]
Embedded PLLs — [DATA_NEEDED: PLL count]
Config Device Compatibility — [DATA_NEEDED: supported configuration devices]
RoHS — unknown - N suffix may indicate Pb-free, not verified in fetched data

数据手册与资源

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