EP1S20F672I7N vs EP1S20F672C7N 对比

详细并排对比 EP1S20F672I7N 出自 Intel 和 EP1S20F672C7N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1S20F672I7N EP1S20F672C7N
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $198.00 $109.20
Family Stratix Stratix
Logic Elements 18,460 —
Logic Array Blocks (LABs) 1,846 —
Maximum User I/Os 426 —
Embedded Memory (RAM bits) 1,669,248 —
Total Memory Bits 1,669,248 —
Number of I/O Banks 8 —
Process Technology 130 nm CMOS 130 nm CMOS
Core Supply Voltage (VCCINT) 1.5 V —
I/O Supply Voltage (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.3 V —
封装 672-BBGA (FineLine BGA, 35 x 35 mm, 1.27 mm pitch) 672-FBGA (FineLine BGA)
工作温度 0 C to 85 C (Industrial) 0°C to +85°C (commercial)
Operating Frequency (max) 420.17 MHz —
安装类型 Surface Mount (BGA) Surface Mount
MSL 等级 3 (168 hours) [DATA_NEEDED: moisture sensitivity level]
Lead-Free / RoHS Compliant Yes (lead-free finish, RoHS compliant)
Series — Stratix (first generation)
Logic Elements (LEs) — 18,460
Logic Cells — 18,460
Configurable Logic Blocks (CLBs) — 2,132
Embedded Memory (TriMatrix) — 1,669,248 bits (426 Kbit total)
DSP Blocks — 56 (dedicated 18x18 multipliers)
Maximum User I/O — 586
I/O Banks — [DATA_NEEDED: I/O bank count]
PLLs — Up to 12
Maximum Operating Frequency — 420.17 MHz
Core Voltage — 1.5 V
Package Body Size — 35 mm x 35 mm
Ball Pitch — 1.27 mm
Speed Grade — C7 (-7)
Configuration Modes — PS, PPS, FPP, JTAG

数据手册与资源

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