EP1S40B956C6N vs EP1S40B956C6 对比

详细并排对比 EP1S40B956C6N 出自 Intel 和 EP1S40B956C6 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1S40B956C6N EP1S40B956C6
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $1,050.00 $1,078.40
Series Stratix —
Family Altera Stratix (1st generation) Stratix
Process Technology 0.13 µm CMOS 0.13 um CMOS
Logic Elements (LEs) 41,250 —
Logic Array Blocks (LABs) 4,125 4,125
Embedded Memory 3,423,744 bits (~3.4 Mbit) TriMatrix (M512, M4K, M-RAM blocks)
Maximum User I/O 683 —
电源电压 1.425 V to 1.575 V (1.5 V nominal) —
工作温度 0 °C to +85 °C (Commercial) 0C to 85C
封装 956-ball FineLine BGA (FCBGA) BGA-956 (956-BBGA, FCBGA)
Package Dimensions 40 mm x 40 mm —
Ball Pitch 1.27 mm 1.27 mm
Speed Grade C6 (commercial, mid-speed) 6 (commercial, slowest)
Configuration Interface JTAG (IEEE 1149.1), Passive Serial, Active Serial —
安装类型 Surface Mount Surface Mount
MSL 等级 [DATA_NEEDED: MSL rating] —
RoHS 状态 [DATA_NEEDED: RoHS compliance] —
Logic Elements / Cells — 41,250
CLB Equivalents / Registers — 46,970
User I/O Pins — 683
Package Size — 40 x 40 mm
Core Supply Voltage — 1.5 V
Logic Family — CMOS
DSP Blocks — Embedded multiplier blocks
PLLs — Multiple phase-locked loops
Lead-Free / RoHS — Per Altera/Intel datasheet

数据手册与资源

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