EP1S40F1020C5 vs EP1S40F1020C5GA 对比

详细并排对比 EP1S40F1020C5 出自 Intel 和 EP1S40F1020C5GA 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1S40F1020C5 EP1S40F1020C5GA
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $165.00 $171.00
Family Stratix —
Series Stratix I Stratix
Logic Elements 41,250 —
Logic Array Blocks (LABs) 4,125 —
Maximum User I/Os 773 —
Embedded Memory 3.4 Mbits (TriMatrix) —
DSP Blocks Yes (dedicated hardware multipliers) Embedded multiplier blocks (count per Stratix datasheet family)
Process Technology 130 nm —
Core Voltage 1.425 V to 1.575 V —
Speed Grade C5 C5
封装 1020-ball FC-FBGA (33 mm x 33 mm) 1020-BBGA (FineLine BGA)
安装类型 Surface Mount (BGA) Surface Mount
工作温度 0C to +85C (Commercial) 0C to +85C (Commercial)
Maximum Internal Clock up to 500 MHz —
I/O Standards Supported LVTTL, LVCMOS, SSTL, HSTL, LVDS, PCI —
RoHS 状态 [DATA_NEEDED: rohs status] Unknown - non-GA suffix commercial part
Logic Elements (LE) — 41,250
Total RAM Bits — 3,423,744
User I/O Count — 773
Process Node — 0.13 µm CMOS with 9-layer metal
Supply Voltage (Core) — [DATA_NEEDED: VCCINT value]
I/O Bank Count — [DATA_NEEDED: bank count]
PLL Count — Up to 12 enhanced PLLs (per Stratix family)
High-Speed Transceivers — Up to 12 channels (per Stratix family, variant dependent)
Configuration Method — JTAG, Passive Serial, Altera EPC device
Lead-Free — Yes (per Altera/Intel policy at release)
MSL 等级 — [DATA_NEEDED: MSL rating]

数据手册与资源

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