EP1S80B956C6AA vs EP1S30B956C6 对比

详细并排对比 EP1S80B956C6AA 出自 Intel 和 EP1S30B956C6 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1S80B956C6AA EP1S30B956C6
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $215.00 $78.00
Family Stratix Stratix
Process Node 130 nm —
Logic Elements 79,040 —
M4K RAM Blocks 742 —
Total Embedded Memory [DATA_NEEDED: total embedded memory bits] —
DSP Blocks [DATA_NEEDED: DSP block count] Yes (Stratix DSP blocks)
User I/O Pins 683 —
封装 956-BGA 956-ball FCBGA (BGA-956), 40 x 40 mm, 1.27 mm pitch
Core Voltage (VCCINT) 1.5 V 1.5 V
I/O Voltage (VCCIO) MultiVolt (1.5 V, 1.8 V, 2.5 V, 3.3 V) —
Speed Grade C6 C6
工作温度 Commercial (0C to +85C) - inferred from C6 suffix 0 C to 85 C (Commercial)
Configuration Scheme Active Serial / Passive Serial / JTAG —
PLLs 6 Up to 12
安装类型 Surface Mount (BGA) Surface Mount
RoHS 状态 Lead free / RoHS Compliant Not confirmed - pre-RoHS part
Legacy Status Obsolete - Mult Device EOL 1/Jun/2017 —
Logic Elements (LEs) — 32,470
Logic Array Blocks (LABs) — 3,247
Embedded Memory Bits — 3,317,184 (approximately 3.4 Mbit)
Maximum User I/O — 683
Process Technology — 130 nm CMOS
Maximum Internal Frequency — 450.05 MHz (per family datasheet)
Configuration Modes — Passive Serial (PS), Passive Parallel (PP), JTAG
MSL 等级 — [DATA_NEEDED: MSL level]
Lead-Free — Unknown

数据手册与资源

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