EP1SGX25DF67216 vs EP1SGX25CF672C6N 对比

详细并排对比 EP1SGX25DF67216 出自 Altera 和 EP1SGX25CF672C6N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1SGX25DF67216 EP1SGX25CF672C6N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $198.00 $210.00
Family Stratix GX Stratix GX
Logic Elements 25,660 25,660
Total RAM Bits 1,944,576 —
Embedded Multipliers (18x18) [DATA_NEEDED: 18x18 multiplier count] —
Number of PLLs 4 —
Number of Transceiver Channels 8 (4 in each of 2 banks) —
Max Transceiver Data Rate 3.1875 Gbps per channel —
Min Transceiver Data Rate 500 Mbps —
Core Supply Voltage 1.5 V —
Auxiliary Supply Voltage 3.3 V —
I/O Supply Voltage 1.5 V / 1.8 V / 2.5 V / 3.3 V (per bank) —
Maximum User I/O Pins [DATA_NEEDED: user I/O count for DF672 package] —
封装 672-ball FineLine BGA (DF672) 672-ball FBGA (FineLine BGA)
安装类型 Surface Mount (BGA) Surface Mount
工作温度 Industrial, -40C to +100C (I-suffix family) 0 °C to +85 °C
On-Die Termination Yes, 100-ohm differential —
Pre-emphasis / Equalization Programmable (transmitter pre-emphasis; receiver adaptive equalization) —
Configuration Schemes Passive serial, fast passive parallel, JTAG, Altera enhanced configuration —
RoHS 状态 Lead-free / RoHS compliant (per Altera product family documentation) Compliant
Configurable Logic Blocks (CLBs) — 2,852
Logic Array Blocks (LABs) — 2,566
Embedded Memory (bits) — 1,944,576
Maximum User I/O — 455
Process Technology — 130 nm CMOS
Core Voltage (VCCINT) — 1.5 V
Speed Grade — -6 (commercial)
Package Size — 27 x 27 mm
Ball Pitch — 1.0 mm
Lead-Free — Yes

数据手册与资源

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