EP1SGX25DF672I7N vs EP1SGX25DF67216 对比
详细并排对比 EP1SGX25DF672I7N 出自 Intel 和 EP1SGX25DF67216 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1SGX25DF672I7N | EP1SGX25DF67216 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $162.00 | $198.00 |
| Family | Stratix GX | Stratix GX |
| Logic Elements | 25,660 | 25,660 |
| CLBs | 2,566 | — |
| Maximum Operating Frequency | 4385.97 MHz (logic); 4.7 MHz (combinatorial CLB delay rating) | — |
| Combinatorial Delay (CLB) | 9.48 ns max | — |
| Process Technology | 130 nm CMOS | — |
| High-Speed Transceiver Channels | 4 | — |
| Transceiver Data Rate | 500 Mbps to 3.1875 Gbps per channel | — |
| Core Supply Voltage (VCCINT) | 1.5 V | — |
| Supply Voltage Range | 1.425 V to 1.575 V | — |
| 封装 | 672-ball FineLine BGA (FC-FBGA), 33 × 33 mm, 1 mm pitch | 672-ball FineLine BGA (DF672) |
| Logic Family | CMOS | — |
| 工作温度 | 0 °C to 85 °C (industrial) | Industrial, -40C to +100C (I-suffix family) |
| Lead-Free | Yes | — |
| RoHS 状态 | [DATA_NEEDED: rohs status] | Lead-free / RoHS compliant (per Altera product family documentation) |
| 安装类型 | Surface Mount (BGA) | Surface Mount (BGA) |
| Terminal Form | Ball (BGA) | — |
| Number of Terminals | 672 | — |
| Total RAM Bits | — | 1,944,576 |
| Embedded Multipliers (18x18) | — | [DATA_NEEDED: 18x18 multiplier count] |
| Number of PLLs | — | 4 |
| Number of Transceiver Channels | — | 8 (4 in each of 2 banks) |
| Max Transceiver Data Rate | — | 3.1875 Gbps per channel |
| Min Transceiver Data Rate | — | 500 Mbps |
| Core Supply Voltage | — | 1.5 V |
| Auxiliary Supply Voltage | — | 3.3 V |
| I/O Supply Voltage | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (per bank) |
| Maximum User I/O Pins | — | [DATA_NEEDED: user I/O count for DF672 package] |
| On-Die Termination | — | Yes, 100-ohm differential |
| Pre-emphasis / Equalization | — | Programmable (transmitter pre-emphasis; receiver adaptive equalization) |
| Configuration Schemes | — | Passive serial, fast passive parallel, JTAG, Altera enhanced configuration |