EP1SGX40DF1020C7ES vs EP1SGX40CF1020I5 对比

详细并排对比 EP1SGX40DF1020C7ES 出自 Altera 和 EP1SGX40CF1020I5 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1SGX40DF1020C7ES EP1SGX40CF1020I5
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $1,325.00 $370.00
Family Stratix GX Stratix (first generation)
Logic Elements 41,250 41,250
Logic Family CMOS —
Process Technology 130 nm CMOS
电源电压 1.5 V (core) —
封装 FBGA-1020 (33 x 33 mm, 1.0 mm pitch) —
Terminal Form Ball —
Package Shape Square —
Number of Pins/Terminals 1020 —
工作温度 0 C to 85 C (32 F to 185 F) -40C to +100C (industrial, I suffix)
Temperature Grade Commercial (speed grade C7) —
安装类型 Surface Mount (BGA) Surface Mount
Combinatorial Delay 9.48 ns per CLB —
最大时钟频率 4385.97 MHz (internal) —
Manufacturer Altera (now Intel PSG) —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: confirmed RoHS per Intel/Altera]
Series — Stratix GX
Configurable Logic Blocks (CLBs) — 4,125
Total RAM Bits — 3,423,744
Number of Logic Cells / Gates — [DATA_NEEDED: gate count equivalent]
Supply Voltage (Core) — 1.5 V
Number of Transceivers — 624 (per DigiKey listing family variant)
Number of I/O Pins — [DATA_NEEDED: user I/O count]
Package Type — FBGA-1020 (FineLine BGA)
Package Dimensions — 33 mm x 33 mm
Ball Pitch — 1.0 mm
Configuration Memory — SRAM-based (external config device required)
Speed Grade — 5
Device Family Suffix Decoding — C = standard logic, F = enhanced, I = industrial temp

数据手册与资源

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