EP1SGX40GF1020C7N vs EP1SGX40CF1020I5 对比

详细并排对比 EP1SGX40GF1020C7N 出自 Altera 和 EP1SGX40CF1020I5 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1SGX40GF1020C7N EP1SGX40CF1020I5
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $285.00 $370.00
Series Stratix GX Stratix GX
Family Stratix (1st generation, GX sub-family) Stratix (first generation)
Logic Elements (LEs) 41,250 —
Logic Array Blocks (LABs) 4,125 —
Total RAM Bits 3,423,744 3,423,744
User I/O Count 624 —
Core Supply Voltage 1.425 V to 1.575 V (1.5 V nominal) —
Logic Family CMOS —
Process Technology 0.13 um CMOS CMOS
工作温度 0 C to 85 C (Commercial) -40C to +100C (industrial, I suffix)
Package Type 1020-ball FineLine BGA (FBGA) FBGA-1020 (FineLine BGA)
Package Dimensions 33 x 33 mm, 1.0 mm pitch 33 mm x 33 mm
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: confirmed RoHS per Intel/Altera]
Lead-Free [DATA_NEEDED: lead-free status] —
Configuration Modes Active Serial, Passive Serial, JTAG —
Speed Grade C7 (commercial, fastest) 5
MSL 等级 [DATA_NEEDED: MSL rating] —
Logic Elements — 41,250
Configurable Logic Blocks (CLBs) — 4,125
Number of Logic Cells / Gates — [DATA_NEEDED: gate count equivalent]
Supply Voltage (Core) — 1.5 V
Number of Transceivers — 624 (per DigiKey listing family variant)
Number of I/O Pins — [DATA_NEEDED: user I/O count]
Ball Pitch — 1.0 mm
Configuration Memory — SRAM-based (external config device required)
Device Family Suffix Decoding — C = standard logic, F = enhanced, I = industrial temp

数据手册与资源

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