EP20K1000CF33C9ES vs EP20K1000CF33I8N 对比
详细并排对比 EP20K1000CF33C9ES 出自 Altera 和 EP20K1000CF33I8N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP20K1000CF33C9ES | EP20K1000CF33I8N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 最后采购期 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $215.00 | $210.00 |
| Family | APEX-20KC | APEX 20KC |
| Manufacturer | Intel (formerly Altera) | — |
| Typical Gate Count | 1,000,000 system gates | — |
| Logic Elements | 38,400 | 38,400 cells |
| Logic Array Blocks (LABs) | 3,840 | — |
| Embedded System Blocks (ESBs) | 212 | — |
| Total Embedded RAM Bits | 327,680 bits | — |
| Maximum User I/O Pins | 708 | — |
| 封装 | 1,020-ball FineLine BGA (FBGA) | — |
| Speed Grade | C9 | I8 |
| 工作温度 | 0 C to +85 C (commercial) | -40 °C to +85 °C (industrial) |
| Process Technology | 0.18 um CMOS | 0.15 µm CMOS |
| Logic Element Architecture | 4-input LUT with dedicated carry chain | — |
| Maximum Embedded RAM per ESB | 32,768 bits (dual-port, FIFO support) | — |
| Phase-Locked Loops | Up to 4 enhanced PLLs | — |
| MultiVolt I/O Support | 1.8V / 2.5V / 3.3V / 5.0V | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Configuration Method | Passive serial / Passive parallel / JTAG | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs status] |
| Lead-Free | [DATA_NEEDED: lead-free finish status] | — |
| System Gates | — | 1,000,000 (approx.) |
| Maximum Internal Clock Frequency | — | 301.21 MHz |
| Propagation Delay | — | 1.79 ns |
| Number of Logic Elements / Cells | — | 38,400 |
| Core Supply Voltage | — | 1.8 V nominal (1.71 V to 1.89 V) |
| Number of I/O Pins | — | 700 user I/O |
| 引脚数 | — | 1020 |
| Package Type | — | FC-FBGA-1020 (Flip-Chip Fine-pitch BGA) |
| Embedded Memory | — | Dual-port RAM via ESB blocks |
| PLL Count | — | 4 |
| Configuration Interface | — | IEEE 1149.1 JTAG, EPC serial/parallel |
| 安装类型 | — | Surface Mount |