EP20K100EFC324-1N vs EP20K30EFC324-1X 对比

详细并排对比 EP20K100EFC324-1N 出自 Altera 和 EP20K30EFC324-1X 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K100EFC324-1N EP20K30EFC324-1X
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $108.00 $3.30
Family APEX-20KE APEX-20K® (MultiCore™ architecture)
Device Type FPGA (Field Programmable Gate Array) —
Logic Elements (LEs) 4160 1,200
Typical Gates 100,000 —
Maximum User I/O 246 128
Embedded System Blocks (ESBs) 53248 bits —
封装 324-BGA (FineLine BGA) 324-ball FBGA (FineLine BGA), 19x19 mm
工作温度 0 C to 85 C —
Propagation Delay 1.6 ns —
Internal Operating Frequency 250 MHz —
Core Voltage 1.8 V —
I/O Standard Support LVDS, SSTL, HSTL, LVTTL, LVCMOS LVDS, LVTTL, LVCMOS, PCI, SSTL
Process Technology 0.15 µm all-layer copper CMOS 0.22 µm CMOS
JTAG Support IEEE 1149.1 boundary-scan —
Programming Technology SRAM-based (volatile, requires configuration device) —
MultiVolt I/O 1.8 V core with 3.3 V / 5.0 V I/O support —
Series — APEX 20KE
Typical Gate Count — 30,000 gates
Embedded Memory (RAM bits) — 24,576
Dedicated Inputs — 4
Core Supply Voltage — 1.71 V to 1.89 V (1.8 V nominal)
Logic Delay (tPD) — 1.91 ns
最大时钟频率 — 909 MHz (internal), 160 MHz (I/O per partstack summary)
安装类型 — Surface Mount
Configuration Method — Passive Serial, JTAG, Fast Passive Parallel
PLLs — 4
RoHS 状态 — Compliant
Operating Temperature Grade — Commercial (0 °C to +85 °C) per package suffix interpretation; industrial on -1X grade [DATA_NEEDED: exact Tj range]

数据手册与资源

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