EP20K200BC484-1X vs EP20K200CF484C7 对比
详细并排对比 EP20K200BC484-1X 出自 Altera 和 EP20K200CF484C7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EP20K200BC484-1X - APEX-20K 200K-Gate FPGA 382 I/O 484-BGA | Altera
EP20K200BC484-1X Obsolete规格对比
| 参数 | EP20K200BC484-1X | EP20K200CF484C7 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $75.10 | $82.00 |
| Product Family | APEX-20K | — |
| Series | EP20K200 | APEX 20KC |
| Logic Elements / Cells | 8320 | — |
| Total RAM Bits | 106496 | 106,496 |
| Number of I/O | 382 | 376 |
| Number of Logic Gates | 200000 | — |
| Package Type | 484-BBGA (Fine-pitch Ball Grid Array) | — |
| Package Suffix | BC484 | — |
| Speed Grade | -1 (slowest commercial grade) | C7 (commercial, mid-performance) |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度 | 0C to +85C (commercial, [DATA_NEEDED: full Tjj range]) | 0°C to +85°C |
| Configuration Method | SRAM - external serial/parallel PROM | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| PLL | ClockLock / ClockBoost | — |
| Embedded Memory Blocks | Embedded System Blocks (ESBs) - RAM/ROM/CAM | — |
| MSL 等级 | [DATA_NEEDED: MSL level] | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | APEX 20KC |
| Number of Logic Elements (LEs) | — | 8,320 |
| Number of Gates | — | 200,000 |
| Supply Voltage - Core | — | 1.71 V to 1.89 V |
| Process Technology | — | 0.15 µm CMOS, Copper interconnect |
| Maximum Internal Frequency | — | 375.94 MHz |
| LVDS Support | — | Yes |
| 封装 / 外壳 | — | 484-BBGA (FineLine BGA, 23×23 mm) |
| Supplier Device Package | — | 484-FBGA |
| Configuration Memory | — | SRAM-based (volatile, requires configuration device) |