EP20K200CF484I9 vs EP20K200CF484I9N 对比
详细并排对比 EP20K200CF484I9 出自 Altera 和 EP20K200CF484I9N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP20K200CF484I9 | EP20K200CF484I9N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $138.00 | $115.00 |
| Series | APEX 20KC | — |
| Family | APEX 20KC (APEX 20K with ESB/CAM) | APEX 20KC |
| Process Technology | 0.15 um CMOS | 0.15 µm CMOS |
| Typical Gates | 200,000 | — |
| Logic Elements (Cells) | 8,320 | — |
| Maximum User I/O | 376 | — |
| Dedicated Inputs | 4 | — |
| Total Terminals | 484 (balls) | — |
| 封装 | 484-ball FineLine BGA (FBGA), 1.00 mm pitch | 484-pin FBGA (PBGA484), 1.0 mm pitch |
| Core Supply Voltage (VCCINT) | 1.8 V nominal (1.71 V to 1.89 V) | — |
| Operating Temperature Grade | Industrial (I) | — |
| Junction Temperature Range | -40 C to +100 C | — |
| Speed Grade | -9 (lowest speed in EP20K200 family) | I9 (industrial, highest-performance bin) |
| Configuration Method | SRAM, JTAG in-system programmable | — |
| RoHS 状态 | unknown - confirm with supplier (legacy part) | Compliant |
| Lifecycle | Obsolete - EOL announced by Altera/Intel in 2008 | — |
| Logic Elements / Cells | — | 8,320 |
| Maximum Gates | — | 200,000 |
| Maximum Internal Frequency | — | 250 MHz |
| Core Supply Voltage | — | 1.8 V nominal (1.71 V to 1.89 V) |
| User I/O Count | — | 376 (368 user I/O + 4 dedicated inputs) |
| 工作温度 | — | [DATA_NEEDED: industrial temperature range -40C to +85C assumed for I-grade] |
| Programmable I/O Standards | — | LVTTL, LVCMOS, PCI |
| Configuration Interface | — | JTAG IEEE 1149.1, ByteBlaster/BitBlaster serial |
| On-chip Memory | — | Embedded System Blocks (ESBs) for distributed RAM/ROM |
| Lead-Free (Pb-free) | — | Yes (N suffix) |