EP20K200EBC356-1N vs EP20K200BC356-1 对比
详细并排对比 EP20K200EBC356-1N 出自 Intel 和 EP20K200BC356-1 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP20K200EBC356-1N | EP20K200BC356-1 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $171.00 | $335.00 |
| Family | APEX 20KE | — |
| Series | APEX-20KE | — |
| Logic Elements / Cells | 8,320 | 8320 |
| Typical Gates | 200,000 | — |
| Number of Macrocells | 832 | — |
| User I/Os | 271 | — |
| Propagation Delay | 2.5 ns | — |
| Internal Frequency (max) | 367 MHz | — |
| Process Technology | 0.22 um CMOS | 0.22 um |
| Core Supply Voltage (VCCINT) | 1.71 V to 1.89 V (nominal 1.8 V) | — |
| I/O Supply Voltage | MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V | — |
| 封装 | 356-BGA (LBGA, 35 x 35 mm) | — |
| 工作温度 | 0 C to +85 C (commercial) | — |
| 安装类型 | Surface Mount | Surface Mount |
| MSL 等级 | 3 (168 hours) | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS/lead finish of original non-N EP20K200BC356-1] |
| Logic Family / Architecture | CMOS, MultiCore (LUT + embedded memory) | — |
| Configuration Method | SRAM-based, in-system programmable | — |
| Product Function | — | APEX-20K Field Programmable Gate Array (FPGA) |
| Logic Family | — | CMOS |
| Equivalent System Gates | — | 200K gates |
| Total RAM Bits | — | 106496 bits |
| 最大时钟频率 | — | 250 MHz |
| Core Supply Voltage | — | 2.5 V |
| User I/O Count | — | 277 |
| 引脚数 | — | 356 |
| 封装 / 外壳 | — | 356-LBGA |
| Package Code | — | LBGA |
| Package Shape | — | Square |
| Propagation Delay (tPD) | — | 2.5 ns (from -1N variant listing) |
| 工作温度范围 | — | 0 to 85 C (commercial, per -1N variant listing) |
| Lead-Free Finish | — | [DATA_NEEDED: original non-N finish not specified; N suffix indicates lead-free] |